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twindie ? 1.35v ddr3l sdram MT41K2G4 C 128 meg x 4 x 8 banks x 2 ranks mt41k1g8 C 64 meg x 8 x 8 banks x 2 ranks description the 8gb (twindie ? ) ddr3l sdram (1.35v) uses microns 4gb ddr3l sdram die (essentially two ranks of the 4gb ddr3l sdram). refer to microns 4gb ddr3 sdram data sheet for the specifications not included in this document. specifications for base part number mt41k1g4 correlate to twindie manu- facturing part number MT41K2G4; specifications for base part number mt41k512m8 correlate to twindie manufacturing part number mt41k1g8. features ? uses 4gb micron die ? two ranks (includes dual cs#, odt, cke, and zq balls) ? each rank has eight internal banks for concurrent operation ? v dd = v ddq = 1.35v (1.283C1.45v); backward com- patible to v dd = v ddq = 1.5v 0.075v ? 1.35v center-terminated push/pull i/o ? jedec-standard ball-out ? low-profile package ? t c of 0c to 95c C 0c to 85c: 8192 refresh cycles in 64ms C 85c to 95c: 8192 refresh cycles in 32ms C industrial temperature (it) available (rev. e) options marking ? configuration C 128 meg x 4 x 8 banks x 2 ranks 2g4 C 64 meg x 8 x 8 banks x 2 ranks 1g8 ? fbga package (pb-free) C 78-ball fbga (10.5mm x 12mm x 1.2mm) die rev :d the C 78-ball fbga (9.5mm x 11.5mm x 1.2mm) die rev :e trf ? timing C cycle time 1 C 1.071ns @ cl = 13 (ddr3l-1866) -107 C 1.25ns @ cl = 11 (ddr3l-1600) -125 C 1.5ns @ cl = 9 (ddr3l-1333) -15e C 1.87ns @ cl = 7 (ddr3l-1066) -187e ? self refresh C standard none ? operating temperature C commercial (0c t c 95c) none C industrial (-40c t c 95c) rev. e it ? revision :d/:e note: 1. cl = cas (read) latency. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -107 1 , 2 , 3 1866 13-13-13 13.91 13.91 13.91 -125 1 , 2 1600 11-11-11 13.75 13.75 13.75 -15e 1 1333 9-9-9 13.5 13.5 13.5 -187e 1066 7-7-7 13.1 13.1 13.1 notes: 1. backward compatible to 1066, cl = 7 (-187e). 2. backward compatible to 1333, cl = 9 (-15e). 3. backward compatible to 1600, cl = 11 (-125). preliminary ? 8gb: x4, x8 twindie ddr3l sdram description pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved. ?products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet microns production data sheet specifications.
table 2: addressing parameter 2048 meg x 4 1024 meg x 8 configuration 128 meg x 4 x 8 banks x 2 ranks 64 meg x 8 x 8 banks x 2 ranks refresh count 8k 8k row address 64k a[15:0] 64k a[15:0] bank address 8 ba[2:0] 8 ba[2:0] column address 2k a[11, 9:0] 1k a[9:0] preliminary 8gb: x4, x8 twindie ddr3l sdram description pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
ball assignments and descriptions figure 1: 78-ball fbga ball assignments (top view) 4 6 5 a b c d e f g h j k l m n 1 v ss v ss v ddq v ssq v refdq odt1 odt0 cs1# v ss v dd v ss v dd v ss 2 v dd v ssq dq2 nf, dq6 v ddq v ss v dd cs0# ba0 a3 a5 a7 reset# 3 nc dq0 dqs dqs# nf, dq4 ras# cas# we# ba2 a0 a2 a9 a13 7 nf, nf/tdqs# dm, dm/tdqs dq1 v dd nf, dq7 ck ck# a10/ap a15 a12/bc# a1 a11 a14 8 v ss v ssq dq3 v ss nf, dq5 v ss v dd zq0 v refca ba1 a4 a6 a8 9 v dd v ddq v ssq v ssq v ddq cke1 cke0 zq1 v ss v dd v ss v dd v ss note: 1. dark balls (with ring) designate balls that differ from the monolithic versions. preliminary 8gb: x4, x8 twindie ddr3l sdram ball assignments and descriptions pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 3: fbga 78-ball descriptions symbol type description a15, a14, a13, a12/bc#, a11, a10/ap, a[9:0] input address inputs: provide the row address for activate commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge com- mand determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. address inputs are referenced to v refca . a12/bc#: when enabled in the mode register (mr), a12 is sampled during read and write commands to deter- mine whether burst chop (on-the-fly) will be performed (high = burst length (bl) of 8 or no burst chop, low = burst chop (bc) of 4, burst chop). ba[2:0] input bank address inputs: ba[2:0] define the bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, or mr3) is loaded during the load mode command. ba[2:0] are referenced to v refca . ck, ck# input clock: ck and ck# are differential clock inputs. all command, address, and control input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. output data strobe (dqs, dqs#) is referenced to the crossings of ck and ck#. cke[1:0] input clock enable: cke enables (registered high) and disables (registered low) internal cir- cuitry and clocks on the dram. the specific circuitry that is enabled/disabled is depend- ent upon the ddr3l sdram configuration and operating mode. taking cke low pro- vides precharge power-down and self refresh operations (all banks idle) or active power-down (row active in any bank). cke is synchronous for power-down entry and exit and for self refresh entry. cke is asynchronous for self refresh exit. input buffers (exclud- ing ck, ck#, cke, reset#, and odt) are disabled during power-down. input buffers (ex- cluding cke and reset#) are disabled during self refresh. cke is referenced to v refca . cs#[1:0] input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for exter- nal rank selection on systems with multiple ranks. cs# is considered part of the command code. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high, along with the input data, during a write access. although the dm ball is input-only, the dm loading is designed to match that of the dq and dqs balls. dm is referenced to v refdq . dm has an optional use as tdqs on the x8. odt[1:0] input on-die termination: odt enables (registered high) and disables (registered low) ter- mination resistance internal to the ddr3l sdram. when enabled in normal operation, odt is only applied to each of the following balls: dq[7:0], dqs, dqs#, and dm for the x8; dq[3:0], dqs, dqs#, and dm for the x4. the odt input is ignored if disabled via the load mode command. odt is referenced to v refca . ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered and are referenced to v refca . reset# input reset: reset# is an active low cmos input referenced to v ss . the reset# input receiver is a cmos input defined as a rail-to-rail signal with dc high 0.8 v ddq and dc low 0.2 v ddq . reset# assertion and desertion are asynchronous. dq[3:0] i/o data input/output: bidirectional data bus for x4 configuration. dq[3:0] are referenced to v refdq . preliminary 8gb: x4, x8 twindie ddr3l sdram ball assignments and descriptions pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 3: fbga 78-ball descriptions (continued) symbol type description dq[7:0] i/o data input/output: bidirectional data bus for x8 configuration. dq[7:0] are referenced to v refdq . dqs, dqs# i/o data strobe: dqs and dqs# are differential data strobes: output with read data; edge aligned with read data; input with write data; center-aligned with write data. tdqs, tdqs# i/o termination data strobe: applies to the x8 configuration only. when tdqs is enabled, dm is disabled, and the tdqs and tdqs# balls provide termination resistance. v dd supply power supply: 1.35v (1.283v to 1.45v operational; compatible with 1.5v operation) v ddq supply dq power supply: 1.35v (1.283v to 1.45v operational; compatible with 1.5v opera- tion). isolated on the device for improved noise immunity. v refca supply reference voltage for control, command, and address: v refca must be maintained at all times (including self refresh) for proper device operation. v refdq supply reference voltage for data: v refdq must be maintained at all times (including self re- fresh) for proper device operation. v ss supply ground. v ssq supply dq ground: isolated on the device for improved noise immunity. zq[1:0] reference external reference ball for output drive calibration: this ball is tied to an external 240 resistor (rzq), which is tied to v ssq . nc C no connect: these balls should be left unconnected (the ball has no connection to the dram or to other balls). nf C no function: when configured as a x4 device, these balls are nf. when configured as a x8 device, these balls are defined as tdqs#, dq[7:4]. preliminary 8gb: x4, x8 twindie ddr3l sdram ball assignments and descriptions pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
functional description the twindie ddr3l sdram is a high-speed, cmos dynamic random access memory device internally configured as two 8-bank ddr3l sdram devices. although each die is tested individually within the dual-die package, some twindie test results may vary from a like-die tested within a monolithic die package. the ddr3l sdram uses a double data rate architecture to achieve high-speed opera- tion. the double data rate architecture is an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o balls. a single read or write access consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the inter- nal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o balls. the differential data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the ddr3l sdram input receiver. dqs is center-aligned with da- ta for writes. the read data is transmitted by the ddr3l sdram and edge-aligned to the data strobes. read and write accesses to the ddr3l sdram are burst oriented. accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and row to be accessed. the ad- dress bits (including cs n #, ba n , and a n ) registered coincident with the read or write command are used to select the rank, bank, and starting column location for the burst access. this data sheet provides a general description, package dimensions, and the package ballout. refer to the micron monolithic ddr3l data sheet for complete information re- garding individual die initialization, register definition, command descriptions, and die operation. industrial temperature the industrial temperature (it) option, if offered, requires that the case temperature not exceed C40c or 95c. jedec specifications require the refresh rate to double when t c exceeds 85c; this also requires use of the high-temperature self refresh option. addi- tionally, odt resistance, i dd values, some idd specifications and the input/output im- pedance must be derated when t c is < 0c or > 95c. see the ddr3 monolithic data sheet for details. preliminary 8gb: x4, x8 twindie ddr3l sdram functional description pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
functional block diagrams figure 2: functional block diagram (128 meg x 4 x 8 banks x 2 ranks) ras# cas# we# ck ck# dq[3:0] dqs, dqs# dm a[15:0], ba[2:0] cs0# cke0 odt0 rank 0 (128 meg x 4 x 8 banks) rank 1 (128 meg x 4 x 8 banks) cs1# cke1 odt1 zq1 zq0 figure 3: functional block diagram (64 meg x 8 x 8 banks x 2 ranks) tdqs# cas# ras# we# ck ck# dq[7:0] dqs, dqs# dm/tdqs a[15:0], ba[2:0] rank 0 (64 meg x 8 x 8 banks) rank 1 (64 meg x 8 x 8 banks) cs0# cke0 odt0 zq0 cs1# cke1 odt1 zq1 preliminary 8gb: x4, x8 twindie ddr3l sdram functional block diagrams pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
electrical specifications C absolute ratings stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the device data sheet is not implied. exposure to abso- lute maximum rating conditions for extended periods may adversely affect reliability. table 4: absolute maximum dc ratings parameter symbol min max units notes v dd supply voltage relative to v ss v dd C0.4 1.975 v 1 v dd supply voltage relative to v ssq v ddq C0.4 1.975 v voltage on any ball relative to v ss v in , v out C0.4 1.975 v input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) i i C4 4 a v ref supply leakage current v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) i vref C2 2 a 2 operating case temperature t c 0 95 c 3, 4 storage temperature t stg C55 150 c notes: 1. v dd and v ddq must be within 300mv of each other at all times, and v ref must not be greater than 0.6 v ddq . when v dd and v ddq are less than 500mv, v ref may be 300mv. 2. the minimum limit requirement is for testing purposes. the leakage current on the v ref pin should be minimal. 3. max operating case temperature. t c is measured in the center of the package (see fig- ure 4 (page 9)). 4. device functionality is not guaranteed if the dram device exceeds the maximum t c dur- ing operation. temperature and thermal impedance it is imperative that the ddr3l sdram devices temperature specifications, shown in the following table, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the devices thermal impedances cor- rectly. the thermal impedances listed in table 6 (page 9) apply to the current die re- vision and packages. incorrectly using thermal impedances can produce significant errors. read micron technical note tn-00-08, thermal applications, prior to using the values listed in the thermal impedance table. for designs that are expected to last several years and require the flexibility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. the ddr3l sdram devices safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the devices ambient tem- perature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. preliminary 8gb: x4, x8 twindie ddr3l sdram electrical specifications C absolute ratings pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 5: thermal characteristics notes 1C3 apply to entire table parameter symbol value units notes operating temperature t c 0 to 85 c 0 to 95 c 4 notes: 1. max operating case temperature t c is measured in the center of the package, as shown below. 2. a thermal solution must be designed to ensure that the device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of self refresh temperature (srt) or automatic self refresh (asr), if available, must be enabled. figure 4: temperature test point location test point length (l) width (w) 0.5 (w) 0.5 (l) table 6: thermal impedance die rev package substrate ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes d 78-ball low con- ductivity 55.7 42.3 36.8 32 1.5 1 high con- ductivity 35.6 29.3 26.7 23.9 e 78-ball low con- ductivity 57.7 44.1 38.8 20.5 2.1 1 high con- ductivity 36.7 30.6 28.1 18.6 note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. preliminary 8gb: x4, x8 twindie ddr3l sdram electrical specifications C absolute ratings pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
electrical specifications C i cdd parameters table 7: ddr3l i cdd specifications and conditions (rev d) note 1 applies to the entire table combined symbol individual die status bus width -187e -15e -125 units i cdd0 i cdd0 = i dd0 + i dd2p0 x4, x8 75 80 90 ma i cdd1 i cdd1 = i dd1 + i dd2p0 x4 85 90 95 ma x8 92 97 102 i cdd2p0 (slow exit) i cdd2p0 = i dd2p0 + i dd2p0 x4, x8 30 30 30 ma i cdd2p1 (fast exit) i cdd2p1 = i dd2p1 + i dd2p0 x4, x8 43 45 50 ma i cdd2q i cdd2q = i dd2q + i dd2p0 x4, x8 52 57 62 ma i cdd2n i cdd2n = i dd2n + i dd2p0 x4, x8 54 57 62 ma i cdd2n t i cdd2nt = i dd2nt + i dd2p0 x4, x8 55 60 65 ma i cdd3p i cdd3p = i dd3p + i dd2p0 x4, x8 60 65 70 ma i cdd3n i cdd3n = i dd3n + i dd2p0 x4, x8 62 67 72 ma i cdd4r i cdd4rcdd4r = i dd4r + i dd2p0 x4 140 160 180 ma x8 152 172 192 i cdd4w i cdd4w = i dd4w + i dd2p0 x4 120 140 160 ma x8 130 150 170 i cdd5b i cdd5b = i dd5b + i dd2p0 x4, x8 215 220 230 ma i cdd6 i cdd6 = i dd6 + i dd6 x4, x8 36 36 36 ma i cdd6et i cdd6et = i dd6et + i dd6et x4, x8 48 48 48 ma i cdd7 i cdd7 = i dd7 + i dd2p0 x4, x8 215 255 295 ma i cdd8 i cdd8 = 2 i dd2p0 + 4 x4, x8 34 34 34 ma note: 1. i cdd values reflect the combined current of both individual die. i dd x represents individu- al die values. preliminary 8gb: x4, x8 twindie ddr3l sdram electrical specifications C i cdd parameters pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
table 8: ddr3l i cdd specifications and conditions (rev e) note 1 applies to the entire table combined symbol individual die status bus width -187e -15e -125 -107 units i cdd0 i cdd0 = i dd0 + i dd2p0 + 5 x4, x8 67 70 78 85 ma i cdd1 i cdd1 = i dd1 + i dd2p0 + 5 x4 76 80 84 88 ma x8 82 85 89 93 i cdd2p0 (slow exit) i cdd2p0 = i dd2p0 + i dd2p0 x4, x8 36 36 36 36 ma i cdd2p1 (fast exit) i cdd2p1 = i dd2p1 + i dd2p0 x4, x8 44 46 50 55 ma i cdd2q i cdd2q = i dd2q + i dd2p0 x4, x8 45 46 50 53 ma i cdd2n i cdd2n = i dd2n + i dd2p0 x4, x8 46 47 50 53 ma i cdd2n t i cdd2nt = i dd2nt + i dd2p0 x4, x8 50 53 57 60 ma i cdd3p i cdd3p = i dd3p + i dd2p0 x4, x8 50 53 56 59 ma i cdd3n i cdd3n = i dd3n + i dd2p0 x4, x8 50 53 56 59 ma i cdd4r i cdd4rcdd4r = i dd4r + i dd2p0 + 5 x4 136 153 170 187 ma x8 146 163 180 197 i cdd4w i cdd4w = i dd4w + i dd2p0 + 5 x4 110 126 141 156 ma x8 118 133 148 164 i cdd5b i cdd5b = i dd5b + i dd2p0 x4, x8 162 166 173 180 ma i cdd6 i cdd6 = i dd6 + i dd6 x4, x8 40 40 40 40 ma i cdd6et i cdd6et = i dd6et + i dd6et x4, x8 50 50 50 50 ma i cdd7 i cdd7 = i dd7 + i dd2p0 + 5 x4, x8 183 213 243 274 ma i cdd8 i cdd8 = 2 i dd2p0 + 4 x4, x8 40 40 40 40 ma note: 1. i cdd values reflect the combined current of both individual die. i dd x represents individu- al die values. preliminary 8gb: x4, x8 twindie ddr3l sdram electrical specifications C i cdd parameters pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
package dimensions figure 5: 78-ball fbga die rev. d (package code the) seating plane 0.12 a 1 2 3 7 8 9 ball a1 id ball a1 id a 0.25 min 1.1 0.1 6.4 ctr 10.5 0.1 0.8 typ 9.6 ctr 12 0.1 78x ?0.45 dimensions apply to solder balls post-reflow on ?0.35 smd ball pads. 0.8 typ a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). preliminary 8gb: x4, x8 twindie ddr3l sdram package dimensions pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.
figure 6: 78-ball fbga die rev. e (package code trf) seating plane 0.12 a 1 2 3 7 8 9 ball a1 index (covered by sr) ball a1 index a 0.25 min 1.1 0.1 6.4 ctr 9.5 0.1 0.8 typ 9.6 ctr 11.5 0.1 78x ?0.45 dimensions apply to solder balls post-reflow on ?0.33 nsmd ball pads. 0.8 typ a b c d e f g h j k l m n notes: 1. all dimensions are in millimeters. 2. solder ball material: sac305 (96.5% sn, 3% ag, 0.5% cu). 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. preliminary 8gb: x4, x8 twindie ddr3l sdram package dimensions pdf: 09005aef84787542 ddr3l_8gb_x4_x8_2cs_twindie_v70s_v80a.pdf - rev. d 02/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2011 micron technology, inc. all rights reserved.

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